1. Field of the Invention
The present invention relates to the manufacture of integrated circuits and, in particular, to a method and system for determining alignment error of integrated circuit fields within and between circuit layers made by a lithographic process.
2. Description of Related Art
New metrology measurement and lithography control methodologies for overlay control of integrated circuit fields within and between circuit layers made by a lithographic process are described in U.S. Pat. No. 5,877,861. As described therein, exposure tools known as steppers print multiple integrated circuit patterns or fields (also known as product cells) by lithographic methods on successive layers of a semiconductor wafer. These steppers typically pattern different layers by applying step and repeat lithographic exposure or step and scan lithographic exposure in which the full area of the wafer is patterned by sequential exposure of the stepper fields containing one or more integrated circuits. The stepper achieves registration among pattern layers by aligning the current layer to a previously patterned layer. Overlay control methodologies employ metrology structures located in the field kerf outside the integrated circuit fields or product cells to determine alignment and overlay error of the integrated circuit fields within each circuit layer, and between circuit layers made by a lithographic process. The field kerf is the area which separates the individual cells or patterns. To maximize wafer utilization for circuit manufacturing it is desirable to confine the kerf to the width needed to cut apart the cells or patterns upon completion of the printing to produce the individual product chips. Consequently, an objective of overlay control systems is to minimize the size and number of structures required to determine alignment and overlay error. Determination of layer-to-layer overlay error requires a set of metrology structures that interlock between layers. Determination of within-layer overlay error requires a set of metrology structures that interlock between neighboring fields. Combining layer-to-layer and within-layer control implies a doubling of the required overlay metrology structures. The larger amounts of kerf space required to print the added structures, results in less room for product cells, and subsequently product chips, on the wafer. This is shown by way of example in FIG. 13 of the ""861 patent, which shows the numerous different box-in-box structures that are required for intra- and inter-layer alignment and overlay error measurement. It is also noteworthy that the spatial separation of the intra- and inter-layer structures shown in FIG. 13 of the ""861 patent introduces noise to the estimation of overlay correction due to the variation of aberrations over the exposure field. Although the problem of meeting present and future overlay tolerance is an industry-wide issue, the solution to metrology structure space/layout issues, which are raised in implementing the ""861 patent, has not been addressed within the industry.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved system and method of determining overlay error in integrated circuit fields produced by a lithographic process.
A further object of the invention is to provide a system and method for determining overlay error within a single lithographically produced layer and between different lithographically produced layers of an integrated circuit chip.
It another object of the present invention to provide such a system and method for determining overlay error that does not reduce the amount of active circuit area on a semiconductor wafer.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a system of determining alignment error between lithographically produced integrated circuit fields on the same and different lithographic levels. The method comprises creating a first level field layer having a plurality of first level integrated circuit fields and associated set of first level metrology structures adjacent and outside each integrated circuit field. The first level metrology structures include separate first and second structures. A second structure associated with one first level integrated circuit field is located to nest with a first structure associated with an adjacent, first level integrated circuit field when the both first level integrated circuit fields are properly aligned on the same lithographic level. The first level metrology structures further include overlay metrology structures to determine overlay error between the first level field layer and a field layer on another level. The method also includes creating a second level field layer having a plurality of second level integrated circuit fields and associated set of second level metrology structures adjacent and outside each integrated circuit field. The second level metrology structures include separate third and fourth structures. A fourth structure associated with one second level integrated circuit field is located to nest with a third structure associated with an adjacent, second level integrated circuit field when the both second level integrated circuit fields are properly aligned on the same lithographic level. A second level metrology structure of one second level integrated circuit field is located to nest with an overlay metrology structure of the first level integrated circuit field when the first and second level integrated circuit fields are properly aligned on different lithographic levels.
The related method of the present invention comprises determining the locations of common points of reference on the associated first level metrology structures and on the associated second level metrology structures; measuring alignment error of first level integrated circuit fields from the reference point locations of associated first level first and second metrology structures; measuring alignment error of second level integrated circuit fields from the reference point locations of associated second level third and fourth metrology structures; and measuring overlay error between first level and second level integrated circuit fields from the reference point locations of the first level overlay metrology structures and the reference point locations of the second level metrology structures.
Preferably, determining the locations of common points of reference of the metrology structures comprises first locating edges of each of the structures, and subsequently using the location of the edges to calculate centers of each of the structures.
Each integrated circuit field may have an associated set of metrology structures on a side between an adjacent integrated circuit field on the same level. Printed indicia may be provided adjacent each set of metrology structures to identify the integrated circuit field with which the metrology structure set is associated.
In a preferred embodiment, the fourth structures are smaller than the third structures and in the first level overlay structures are larger than the third structures and, a fourth metrology structure of the second level integrated circuit field is adapted to be contained within a third metrology structure of the second level integrated circuit filed, and a third metrology structure of the second level integrated circuit field is adapted to be contained within a first level overlay metrology structure upon proper alignment of integrated circuit fields in each layer and between layers. The first level metrology structures may comprise separate box structures to determine alignment error within the first level, the second level metrology structures may comprise separate box structures to determine alignment error within the second level, and the first level overlay structure may comprise a box structure larger than the second level box structures.
The common points of reference may comprise centers of the metrology structures. The metrology structures are preferably discernable from each other sufficient to determine their centers. The metrology structures may include edges from which may be calculated centers of each of the structures to determine the common points of reference. Preferably, centers of the metrology structures are the same distance, in the x and y directions, from each side of the fields on each level. The first level metrology structures may include first and second structures on opposite sides of the associated first level integrated circuit field, and the second level metrology structures may include third and fourth structures on opposite sides of the associated second level integrated circuit field. The first level metrology structures may also include first and second structures near opposite ends of a side of the associated first level integrated circuit field, and the second level metrology structures may also include third and fourth structures near opposite ends of a side of the associated second level integrated circuit field.